1. Field of the Invention
The present invention relates to a method of fabricating semiconductor devices, and more particularly, to a method of fabricating strained-silicon transistors.
2. Description of the Prior Art
The performance of MOS transistors has increased year after year with the diminution of critical dimensions and the advance of large-scale integrated circuits (LSI). However, it has been recently pointed out that the miniaturization attained by a lithographic technology has reached its limit. Therefore, how to improve the carrier mobility so as to increase the speed performance of MOS transistors has become a major topic for study in the semiconductor field. For the known arts, attempts have been made to use a strained silicon layer, which has been grown epitaxially on a silicon substrate with a silicon germanium (SiGe) layer disposed therebetween. In this type of MOS transistor, a biaxial tensile strain occurs in the epitaxy silicon layer due to the silicon germanium which has a larger lattice constant than silicon, and, as a result, the band structure alters, and the carrier mobility increases. This enhances the speed performance of the MOS transistors.
However, the above technique still suffers the following disadvantages. First, the silicon germanium is deposited across the substrate, making it harder to optimize NMOS and PMOS transistors separately. Second, the silicon germanium layer has poor thermal conductivity. Another concern is that some dopants diffuse more rapidly through the SiGe layer, resulting in a sub-optimum diffusion profile in the source/drain region. Moreover, despite the fact that the SiGe deposited into the predetermined source/drain region via a selective epitaxial growth (SEG) will increase the electron hole mobility of strained-silicon PMOS transistors, the process however will simultaneously decrease the electron mobility of NMOS transistors and influence the overall effectiveness of the transistor.
Preferably, a method commonly used by the industry to increase the electron mobility of NMOS transistors involves depositing a high tensile stress film composed of silicon nitride or silicon oxide over the surface of the NMOS transistors. Consequently, the stress of the high tensile stress film can be utilized to expand the lattice arrangement of the semiconductor substrate underneath the NMOS transistor and at the same time, increase the electron mobility of NMOS transistors.
Please refer to FIG. 1 through FIG. 3. FIG. 1 through FIG. 3 are perspective diagrams showing the means of fabricating a strained-silicon NMOS transistor according to the prior art. As shown in FIG. 1, a semiconductor substrate 10 is provided and a gate structure 12 is formed on the semiconductor substrate 10, in which the gate structure 12 includes a gate oxide layer 14, a gate 16 disposed on the gate oxide layer 14, a cap layer 18 disposed on the gate 16, and an oxide-nitride-oxide (ONO) offset spacer 20. Preferably, the gate oxide layer 14 is composed of silicon dioxide, the gate 16 is composed of doped polysilicon, and the cap layer 18 is composed of silicon nitride to protect the gate 16. Additionally, a shallow trench isolation (STI) 22 is formed around the active area of the gate structure 21 within the semiconductor substrate 10.
As shown in FIG. 2, an ion implantation process is performed to form a source/drain region 26 in the semiconductor substrate 10 around the spacer 20. Next, a rapid thermal annealing (RTA) process is performed to activate the dopants within the source/drain region 26 and repair the damage of the lattice structure of the semiconductor substrate 10 resulting from the ion implantation process.
As shown in FIG. 3, a high tensile stress film 28 composed of silicon nitride or silicon oxide is disposed over the surface of the gate structure 12 and the source/drain region 26. Subsequently, another rapid thermal annealing process is performed to expand the semiconductor substrate 10 underneath the gate 16, such as the lattice arrangement in the channel region, to increase the electron mobility of the strained silicon NMOS transistor.
Since the conventional method of forming high tensile stress film 28 involves disposing a high tensile stress film 28 over the surface of the gate structure 12 and the source/drain region 26 of the NMOS transistor, the stress of the high tensile stress film 28 utilized for increasing the electron mobility of NMOS transistor however will be strongly limited by the block of the spacer 20. Consequently, the effect will become much more obvious in the semiconductor fabrication under 62 nm or below.